A static random access memory device (SRAM) may be used to store binary data. An SRAM device may be constructed from a number of memory cells, wherein each memory cell stores a single bit of data, that is a value of zero (0) or a value of one (1).
A memory cell may be constructed from two inverters (not-gates) that are cross-coupled. In this way, the output (high or low) of the first inverter is the opposite of the input of that inverter. That output is fed to the second inverter, which inverts it and feeds the value as input to the first inverter. Since there are two possible values and two inverters, any value input will persist in the circuit as long as it is powered.
Exemplary SRAM configurations may include memory cells with, for example, 4 transistor cells (4T), 6 transistor (6T) cells, 8 transistor (8T) cells or 10 transistor (10T) cells, as well as other hybrid designs. In various memory SRAM configurations, inverters may be created by using two connected transistors, one pull-up transistor (a PMOS transistor) and one pull-down transistor (an NMOS transistor). The cross-coupled inverter pair itself is thereby comprised of two PMOS transistors and two NMOS transistors. Two further NMOS transistors may be used to regulate access to the memory cell; these are known as access or pass-gate transistors. This layout comprising six transistors is known as a 6T cell or a 6T topology.
There are a number of known ways of creating 6T SRAM memory cells, and these may be dependent on different factors, such as processing capability of the technology, performance, density, power, and functional objectives. A summary of known bit cell topologies is provided by Ishida and shown in FIG. 1. I. M. Ishida, T. Kawakami, A. Tsuji, N. Kawamoto, M. Motoyoshi, and N. Ouchi. “A novel 6t-sram cell technology designed with rectangular patterns scalable beyond 0.18 & generation and desirable for ultra high speed operation”. In Proc. International Electron Devices Meeting IEDM '98 Technical Digest, pages 201-204, 6-9 Dec. 1998.
When scaling a 6T cell below 90 nm, the lithographic challenges in printing and controlling the dimensions within the same printed layer in orthogonal directions has become increasingly difficult. This has led to a restriction in layout for printed layers that require extremely tight control in printed dimension. For the SRAM devices it is therefore advantageous for the active single crystal regions and gate layer to be printed orthogonally thus allowing tight dimensional control for these layers.
One important source of mismatch can be attributed to the “jogs” in the printed design, as are typically needed and used in the type-4 cell design in the active silicon printed pattern. Such “jogs” may be necessary in current designs, for example, to provide different widths of an active region spanning pull down and access (pass gate) transistors, as shown in FIG. 2-3. In general, wider active areas are needed at the pull down transistor, compared to the access transistor to maintain stability during read operations, and wider active areas are needed at the access transistor, compared to the pull up transistor, to maintain stability during write operations. As also shown in FIGS. 3-4, these “jogs” will print with some degree of corner rounding leading to an extended region of non uniformity. Normal corner rounding that occurs during the fabrication process leads to alignment sensitivity for the PD device width. This sensitivity is asymmetrical, such that the left and right PD devices become more different with misalignment. When alignment of the next printed level intersects the region near the jog where rounding has occurred, a non uniform channel will be created and because of the symmetry associated with the industry standard Type-4 topology, device mismatch between the right and left side of the bit cell is created, e.g. between N3 and N4 shown in FIG. 4. The devices circled exhibit different width characteristics and the width of N3 is effectively less than that of N4.
Other non-linear features used in some known designs, such as the M1 lines in the topology shown in FIG. 5, can also increase scaling difficulties and/or induce irregularities in memory cells.
Embodiments of the present invention include memory cell configurations and topologies that overcome some of these and/or other known limitations in the area of memory cell design, and SRAM designs in particular.